32-bit RISC-V Forth for microcontrollers

Devlog 5 Testing The Implementation

November 19, 2022

  1. Testing the implementation
  2. Log 5
  3. Loading the ELF program
  4. Closing Thoughts

Testing the implementation

One of my favourite RISC-V simulators is called Ripes, it is open source and runs entirely offline from a single AppImage file. It’s perfect for testing and single-stepping through an ELF program and visually observing the registers and memory addresses.

Log 5

I wanted to use Ripes but I realized it would be easier to log output through GDB, so let’s start there.

Loading the ELF program

First we’ll want to load the ELF program into qemu:

qemu-system-riscv32 -machine sifive_e -kernel fiveforths.elf -S -s

In another terminal, we’ll run GDB and ensure to load our program in QEMU.

Reading symbols from fiveforths.elf...
(gdb) target remote :1234
Remote debugging using :1234
0x00001004 in ?? ()
(gdb) info reg pc
pc             0x1004	0x1004
(gdb) load
Loading section .text, size 0x290 lma 0x8000000
Start address 0x08000048, load size 656
Transfer rate: 5248 bits in <1 sec, 656 bytes/write.
(gdb) info reg pc
pc             0x8000048	0x8000048 <_start>

That’s better, but since the Assembly code is incomplete and we’re not running it on the Longan Nano Lite, we won’t be able to access memory at that address (0x8000048), so we won’t be able to step through the program… unless I missed something?

You can confirm that it works in Ripes where the first two instructions load __stacktop into the sp register and then the program stops.

There might be some relocation necessary if I want to successfully test this program in qemu/gdb, but for now this is acceptable until I physically connect the MCU.

Closing thoughts

This was a relatively short session with no changes to the source code, so in the next one I’ll jump right into coding the missing words.